| t1000-simple-atomic.py (9802:eec242a5252d) | t1000-simple-atomic.py (9826:014ff1fbff6d) |
|---|---|
| 1# Copyright (c) 2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 17 unchanged lines hidden (view full) --- 26# 27# Authors: Ali Saidi 28 29import m5 30from m5.objects import * 31m5.util.addToPath('../configs/common') 32import FSConfig 33 | 1# Copyright (c) 2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 17 unchanged lines hidden (view full) --- 26# 27# Authors: Ali Saidi 28 29import m5 30from m5.objects import * 31m5.util.addToPath('../configs/common') 32import FSConfig 33 |
| 34system = FSConfig.makeSparcSystem('atomic', SimpleMemory) | 34system = FSConfig.makeSparcSystem('atomic') |
| 35system.clk_domain = SrcClockDomain(clock = '1GHz') 36system.cpu_clk_domain = SrcClockDomain(clock = '1GHz') 37cpu = AtomicSimpleCPU(cpu_id=0, clk_domain = system.cpu_clk_domain) 38system.cpu = cpu 39# create the interrupt controller 40cpu.createInterruptController() 41cpu.connectAllPorts(system.membus) 42 | 35system.clk_domain = SrcClockDomain(clock = '1GHz') 36system.cpu_clk_domain = SrcClockDomain(clock = '1GHz') 37cpu = AtomicSimpleCPU(cpu_id=0, clk_domain = system.cpu_clk_domain) 38system.cpu = cpu 39# create the interrupt controller 40cpu.createInterruptController() 41cpu.connectAllPorts(system.membus) 42 |
| 43# create the memory controllers and connect them, stick with 44# the physmem name to avoid bumping all the reference stats 45system.physmem = [SimpleMemory(range = r, 46 conf_table_reported = True) 47 for r in system.mem_ranges] 48for i in xrange(len(system.physmem)): 49 system.physmem[i].port = system.membus.master 50 |
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| 43root = Root(full_system=True, system=system) 44 45m5.ticks.setGlobalFrequency('2GHz') | 51root = Root(full_system=True, system=system) 52 53m5.ticks.setGlobalFrequency('2GHz') |