| 1# Copyright (c) 2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 31 unchanged lines hidden (view full) --- 40cpu = AtomicSimpleCPU(cpu_id=0, clk_domain = system.cpu_clk_domain) 41system.cpu = cpu 42# create the interrupt controller 43cpu.createInterruptController() 44cpu.connectAllPorts(system.membus) 45 46# create the memory controllers and connect them, stick with 47# the physmem name to avoid bumping all the reference stats |
| 48system.physmem = [SimpleMemory(range = r) |
| 49 for r in system.mem_ranges] 50for i in xrange(len(system.physmem)): 51 system.physmem[i].port = system.membus.master 52 53root = Root(full_system=True, system=system) 54 55m5.ticks.setGlobalFrequency('2GHz') |