simple-timing-ruby.py (9826:014ff1fbff6d) simple-timing-ruby.py (9827:f47274776aa0)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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62options.l1i_assoc=2
63options.l2_assoc=2
64options.l3_assoc=2
65
66# this is a uniprocessor only test
67options.num_cpus = 1
68
69cpu = TimingSimpleCPU(cpu_id=0)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 53 unchanged lines hidden (view full) ---

62options.l1i_assoc=2
63options.l2_assoc=2
64options.l3_assoc=2
65
66# this is a uniprocessor only test
67options.num_cpus = 1
68
69cpu = TimingSimpleCPU(cpu_id=0)
70system = System(cpu = cpu, physmem = SimpleMemory(null = True),
71 clk_domain = SrcClockDomain(clock = '1GHz'))
70system = System(cpu = cpu, physmem = SimpleMemory(null = True))
71# Dummy voltage domain for all our clock domains
72system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
73system.clk_domain = SrcClockDomain(clock = '1GHz',
74 voltage_domain = system.voltage_domain)
72
73# Create a seperate clock domain for components that should run at
74# CPUs frequency
75
76# Create a seperate clock domain for components that should run at
77# CPUs frequency
75system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
78system.cpu.clk_domain = SrcClockDomain(clock = '2GHz',
79 voltage_domain = system.voltage_domain)
76
77system.mem_ranges = AddrRange('256MB')
78
79Ruby.create_system(options, system)
80
81# Create a separate clock for Ruby
80
81system.mem_ranges = AddrRange('256MB')
82
83Ruby.create_system(options, system)
84
85# Create a separate clock for Ruby
82system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
86system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
87 voltage_domain = system.voltage_domain)
83
84assert(len(system.ruby._cpu_ruby_ports) == 1)
85
86# create the interrupt controller
87cpu.createInterruptController()
88
89#
90# Tie the cpu cache ports to the ruby cpu ports and

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89assert(len(system.ruby._cpu_ruby_ports) == 1)
90
91# create the interrupt controller
92cpu.createInterruptController()
93
94#
95# Tie the cpu cache ports to the ruby cpu ports and

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