simple-timing-ruby.py (9577:91cac7c9c636) | simple-timing-ruby.py (9790:ccc428657233) |
---|---|
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 54 unchanged lines hidden (view full) --- 63options.l2_assoc=2 64options.l3_assoc=2 65 66# this is a uniprocessor only test 67options.num_cpus = 1 68 69cpu = TimingSimpleCPU(cpu_id=0) 70system = System(cpu = cpu, physmem = SimpleMemory(null = True)) | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 54 unchanged lines hidden (view full) --- 63options.l2_assoc=2 64options.l3_assoc=2 65 66# this is a uniprocessor only test 67options.num_cpus = 1 68 69cpu = TimingSimpleCPU(cpu_id=0) 70system = System(cpu = cpu, physmem = SimpleMemory(null = True)) |
71system.clock = options.sys_clock |
|
71 72Ruby.create_system(options, system) 73 74assert(len(system.ruby._cpu_ruby_ports) == 1) 75 76# create the interrupt controller 77cpu.createInterruptController() 78 --- 15 unchanged lines hidden --- | 72 73Ruby.create_system(options, system) 74 75assert(len(system.ruby._cpu_ruby_ports) == 1) 76 77# create the interrupt controller 78cpu.createInterruptController() 79 --- 15 unchanged lines hidden --- |