simple-timing-ruby.py (8744:cf8fb1aa1b30) simple-timing-ruby.py (8799:dac1e33e07b0)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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79assert(len(system.ruby._cpu_ruby_ports) == 1)
80
81#
82# Tie the cpu cache ports to the ruby cpu ports and
83# physmem, respectively
84#
85cpu.connectAllPorts(system.ruby._cpu_ruby_ports[0])
86
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 70 unchanged lines hidden (view full) ---

79assert(len(system.ruby._cpu_ruby_ports) == 1)
80
81#
82# Tie the cpu cache ports to the ruby cpu ports and
83# physmem, respectively
84#
85cpu.connectAllPorts(system.ruby._cpu_ruby_ports[0])
86
87# Connect the system port for loading of binaries etc
88system.system_port = system.ruby._sys_port_proxy.port
89
87# -----------------------
88# run simulation
89# -----------------------
90
91root = Root(system = system)
92root.system.mem_mode = 'timing'
93
94# Not much point in this being higher than the L1 latency
95m5.ticks.setGlobalFrequency('1ns')
90# -----------------------
91# run simulation
92# -----------------------
93
94root = Root(system = system)
95root.system.mem_mode = 'timing'
96
97# Not much point in this being higher than the L1 latency
98m5.ticks.setGlobalFrequency('1ns')