| simple-timing-ruby.py (8706:b1838faf3bcc) | simple-timing-ruby.py (8732:fd510b6e124d) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 71 unchanged lines hidden (view full) --- 80 81# 82# Tie the cpu cache ports to the ruby cpu ports and 83# physmem, respectively 84# 85cpu.icache_port = system.ruby._cpu_ruby_ports[0].port 86cpu.dcache_port = system.ruby._cpu_ruby_ports[0].port 87 | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 71 unchanged lines hidden (view full) --- 80 81# 82# Tie the cpu cache ports to the ruby cpu ports and 83# physmem, respectively 84# 85cpu.icache_port = system.ruby._cpu_ruby_ports[0].port 86cpu.dcache_port = system.ruby._cpu_ruby_ports[0].port 87 |
| 88# Connect the system port for loading of binaries etc 89system.system_port = system.ruby._sys_port_proxy.port 90 | |
| 91# ----------------------- 92# run simulation 93# ----------------------- 94 95root = Root(system = system) 96root.system.mem_mode = 'timing' 97 98# Not much point in this being higher than the L1 latency 99m5.ticks.setGlobalFrequency('1ns') | 88# ----------------------- 89# run simulation 90# ----------------------- 91 92root = Root(system = system) 93root.system.mem_mode = 'timing' 94 95# Not much point in this being higher than the L1 latency 96m5.ticks.setGlobalFrequency('1ns') |