| simple-timing-ruby.py (8322:19949c6de823) | simple-timing-ruby.py (8436:5648986156db) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 60 unchanged lines hidden (view full) --- 69options.l3_assoc=2 70 71# this is a uniprocessor only test 72options.num_cpus = 1 73 74cpu = TimingSimpleCPU(cpu_id=0) 75system = System(cpu = cpu, physmem = PhysicalMemory()) 76 | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 60 unchanged lines hidden (view full) --- 69options.l3_assoc=2 70 71# this is a uniprocessor only test 72options.num_cpus = 1 73 74cpu = TimingSimpleCPU(cpu_id=0) 75system = System(cpu = cpu, physmem = PhysicalMemory()) 76 |
| 77system.ruby = Ruby.create_system(options, system) | 77Ruby.create_system(options, system) |
| 78 79assert(len(system.ruby._cpu_ruby_ports) == 1) 80 81# 82# Tie the cpu cache ports to the ruby cpu ports and 83# physmem, respectively 84# 85cpu.icache_port = system.ruby._cpu_ruby_ports[0].port 86cpu.dcache_port = system.ruby._cpu_ruby_ports[0].port 87 88# ----------------------- 89# run simulation 90# ----------------------- 91 92root = Root(system = system) 93root.system.mem_mode = 'timing' 94 95# Not much point in this being higher than the L1 latency 96m5.ticks.setGlobalFrequency('1ns') | 78 79assert(len(system.ruby._cpu_ruby_ports) == 1) 80 81# 82# Tie the cpu cache ports to the ruby cpu ports and 83# physmem, respectively 84# 85cpu.icache_port = system.ruby._cpu_ruby_ports[0].port 86cpu.dcache_port = system.ruby._cpu_ruby_ports[0].port 87 88# ----------------------- 89# run simulation 90# ----------------------- 91 92root = Root(system = system) 93root.system.mem_mode = 'timing' 94 95# Not much point in this being higher than the L1 latency 96m5.ticks.setGlobalFrequency('1ns') |