simple-timing-ruby.py (7034:6bf327b128c6) simple-timing-ruby.py (7570:417ef5d444bd)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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36 panic("This script requires system-emulation mode (*_SE).")
37
38# Get paths we might need
39config_path = os.path.dirname(os.path.abspath(__file__))
40config_root = os.path.dirname(config_path)
41m5_root = os.path.dirname(config_root)
42addToPath(config_root+'/configs/common')
43addToPath(config_root+'/configs/ruby')
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 27 unchanged lines hidden (view full) ---

36 panic("This script requires system-emulation mode (*_SE).")
37
38# Get paths we might need
39config_path = os.path.dirname(os.path.abspath(__file__))
40config_root = os.path.dirname(config_path)
41m5_root = os.path.dirname(config_root)
42addToPath(config_root+'/configs/common')
43addToPath(config_root+'/configs/ruby')
44addToPath(config_root+'/configs/ruby/protocols')
45addToPath(config_root+'/configs/ruby/topologies')
46
47import Ruby
48
49parser = optparse.OptionParser()
50
51#
44
45import Ruby
46
47parser = optparse.OptionParser()
48
49#
52# Set the default cache size and associativity to be very small to encourage
53# races between requests and writebacks.
50# Add the ruby specific and protocol specific options
54#
51#
55parser.add_option("--l1d_size", type="string", default="256B")
56parser.add_option("--l1i_size", type="string", default="256B")
57parser.add_option("--l2_size", type="string", default="512B")
58parser.add_option("--l1d_assoc", type="int", default=2)
59parser.add_option("--l1i_assoc", type="int", default=2)
60parser.add_option("--l2_assoc", type="int", default=2)
52Ruby.define_options(parser)
61
62execfile(os.path.join(config_root, "configs/common", "Options.py"))
63
64(options, args) = parser.parse_args()
65
53
54execfile(os.path.join(config_root, "configs/common", "Options.py"))
55
56(options, args) = parser.parse_args()
57
58#
59# Set the default cache size and associativity to be very small to encourage
60# races between requests and writebacks.
61#
62options.l1d_size="256B"
63options.l1i_size="256B"
64options.l2_size="512B"
65options.l3_size="1kB"
66options.l1d_assoc=2
67options.l1i_assoc=2
68options.l2_assoc=2
69options.l3_assoc=2
70
66# this is a uniprocessor only test
67options.num_cpus = 1
68
69cpu = TimingSimpleCPU(cpu_id=0)
71# this is a uniprocessor only test
72options.num_cpus = 1
73
74cpu = TimingSimpleCPU(cpu_id=0)
70system = System(cpu = cpu,
71 physmem = PhysicalMemory())
75system = System(cpu = cpu, physmem = PhysicalMemory())
72
76
73system.ruby = Ruby.create_system(options, system.physmem)
77system.ruby = Ruby.create_system(options, system)
74
75assert(len(system.ruby.cpu_ruby_ports) == 1)
76
77#
78# Tie the cpu cache ports to the ruby cpu ports and
79# physmem, respectively
80#
81cpu.icache_port = system.ruby.cpu_ruby_ports[0].port
82cpu.dcache_port = system.ruby.cpu_ruby_ports[0].port
83
84# -----------------------
85# run simulation
86# -----------------------
87
88root = Root(system = system)
89root.system.mem_mode = 'timing'
90
91# Not much point in this being higher than the L1 latency
92m5.ticks.setGlobalFrequency('1ns')
78
79assert(len(system.ruby.cpu_ruby_ports) == 1)
80
81#
82# Tie the cpu cache ports to the ruby cpu ports and
83# physmem, respectively
84#
85cpu.icache_port = system.ruby.cpu_ruby_ports[0].port
86cpu.dcache_port = system.ruby.cpu_ruby_ports[0].port
87
88# -----------------------
89# run simulation
90# -----------------------
91
92root = Root(system = system)
93root.system.mem_mode = 'timing'
94
95# Not much point in this being higher than the L1 latency
96m5.ticks.setGlobalFrequency('1ns')