simple-timing-ruby.py (6289:a9e7d19871b5) | simple-timing-ruby.py (6870:5707ef3691b5) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 16 unchanged lines hidden (view full) --- 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Steve Reinhardt 28 29import m5 30from m5.objects import * 31 32import ruby_config | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 16 unchanged lines hidden (view full) --- 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Steve Reinhardt 28 29import m5 30from m5.objects import * 31 32import ruby_config |
33ruby_memory = ruby_config.generate("MI_example-homogeneous.rb", 1) | 33ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", 1) |
34 35cpu = TimingSimpleCPU(cpu_id=0) 36system = System(cpu = cpu, 37 physmem = ruby_memory, 38 membus = Bus()) 39system.physmem.port = system.membus.port 40cpu.connectMemPorts(system.membus) 41cpu.clock = '2GHz' 42 43root = Root(system = system) | 34 35cpu = TimingSimpleCPU(cpu_id=0) 36system = System(cpu = cpu, 37 physmem = ruby_memory, 38 membus = Bus()) 39system.physmem.port = system.membus.port 40cpu.connectMemPorts(system.membus) 41cpu.clock = '2GHz' 42 43root = Root(system = system) |