simple-timing-ruby.py (10117:37e333de580f) simple-timing-ruby.py (10120:f5ceb3c3edb6)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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80
81system.mem_ranges = AddrRange('256MB')
82Ruby.create_system(options, system)
83
84# Create a separate clock for Ruby
85system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
86 voltage_domain = system.voltage_domain)
87
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 71 unchanged lines hidden (view full) ---

80
81system.mem_ranges = AddrRange('256MB')
82Ruby.create_system(options, system)
83
84# Create a separate clock for Ruby
85system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
86 voltage_domain = system.voltage_domain)
87
88assert(len(system.ruby._cpu_ruby_ports) == 1)
88assert(len(system.ruby._cpu_ports) == 1)
89
90# create the interrupt controller
91cpu.createInterruptController()
92
93#
94# Tie the cpu cache ports to the ruby cpu ports and
95# physmem, respectively
96#
89
90# create the interrupt controller
91cpu.createInterruptController()
92
93#
94# Tie the cpu cache ports to the ruby cpu ports and
95# physmem, respectively
96#
97cpu.connectAllPorts(system.ruby._cpu_ruby_ports[0])
97cpu.connectAllPorts(system.ruby._cpu_ports[0])
98
99# -----------------------
100# run simulation
101# -----------------------
102
103root = Root(full_system = False, system = system)
104root.system.mem_mode = 'timing'
105
106# Not much point in this being higher than the L1 latency
107m5.ticks.setGlobalFrequency('1ns')
98
99# -----------------------
100# run simulation
101# -----------------------
102
103root = Root(full_system = False, system = system)
104root.system.mem_mode = 'timing'
105
106# Not much point in this being higher than the L1 latency
107m5.ticks.setGlobalFrequency('1ns')