1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 65 unchanged lines hidden (view full) --- 74 voltage_domain = system.voltage_domain) 75 76# Create a seperate clock domain for components that should run at 77# CPUs frequency 78system.cpu.clk_domain = SrcClockDomain(clock = '2GHz', 79 voltage_domain = system.voltage_domain) 80 81system.mem_ranges = AddrRange('256MB') |
82system.piobus = NoncoherentBus() 83Ruby.create_system(options, system, system.piobus) |
84 |
85# Create a separate clock for Ruby 86system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 87 voltage_domain = system.voltage_domain) 88 89assert(len(system.ruby._cpu_ruby_ports) == 1) 90 91# create the interrupt controller 92cpu.createInterruptController() --- 16 unchanged lines hidden --- |