1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 60 unchanged lines hidden (view full) --- 69cpu = TimingSimpleCPU(cpu_id=0) 70system = System(cpu = cpu, physmem = SimpleMemory(null = True), 71 clk_domain = SrcClockDomain(clock = '1GHz')) 72 73# Create a seperate clock domain for components that should run at 74# CPUs frequency 75system.cpu.clk_domain = SrcClockDomain(clock = '2GHz') 76 |
77system.mem_ranges = AddrRange('256MB') 78 |
79Ruby.create_system(options, system) 80 81# Create a separate clock for Ruby 82system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock) 83 84assert(len(system.ruby._cpu_ruby_ports) == 1) 85 86# create the interrupt controller --- 17 unchanged lines hidden --- |