1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 53 unchanged lines hidden (view full) --- 62options.l1i_assoc=2 63options.l2_assoc=2 64options.l3_assoc=2 65 66# this is a uniprocessor only test 67options.num_cpus = 1 68 69cpu = TimingSimpleCPU(cpu_id=0) |
70system = System(cpu = cpu, physmem = SimpleMemory(null = True), 71 clk_domain = SrcClockDomain(clock = '1GHz')) |
72 |
73# Create a seperate clock domain for components that should run at 74# CPUs frequency 75system.cpu.clk_domain = SrcClockDomain(clock = '2GHz') 76 |
77Ruby.create_system(options, system) 78 |
79# Create a separate clock for Ruby 80system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock) 81 |
82assert(len(system.ruby._cpu_ruby_ports) == 1) 83 84# create the interrupt controller 85cpu.createInterruptController() 86 87# 88# Tie the cpu cache ports to the ruby cpu ports and 89# physmem, respectively --- 12 unchanged lines hidden --- |