30a31,33
> from m5.defines import buildEnv
> from m5.util import addToPath
> import os, optparse, sys
32,33c35,36
< import ruby_config
< ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", 1)
---
> if buildEnv['FULL_SYSTEM']:
> panic("This script requires system-emulation mode (*_SE).")
34a38,66
> # Get paths we might need
> config_path = os.path.dirname(os.path.abspath(__file__))
> config_root = os.path.dirname(config_path)
> m5_root = os.path.dirname(config_root)
> addToPath(config_root+'/configs/common')
> addToPath(config_root+'/configs/ruby')
>
> import Ruby
>
> parser = optparse.OptionParser()
>
> #
> # Set the default cache size and associativity to be very small to encourage
> # races between requests and writebacks.
> #
> parser.add_option("--l1d_size", type="string", default="256B")
> parser.add_option("--l1i_size", type="string", default="256B")
> parser.add_option("--l2_size", type="string", default="512B")
> parser.add_option("--l1d_assoc", type="int", default=2)
> parser.add_option("--l1i_assoc", type="int", default=2)
> parser.add_option("--l2_assoc", type="int", default=2)
>
> execfile(os.path.join(config_root, "configs/common", "Options.py"))
>
> (options, args) = parser.parse_args()
>
> # this is a uniprocessor only test
> options.num_cpus = 1
>
37,41c69
< physmem = ruby_memory,
< membus = Bus())
< system.physmem.port = system.membus.port
< cpu.connectMemPorts(system.membus)
< cpu.clock = '2GHz'
---
> physmem = PhysicalMemory())
42a71,85
> system.ruby = Ruby.create_system(options, system.physmem)
>
> assert(len(system.ruby.cpu_ruby_ports) == 1)
>
> #
> # Tie the cpu cache ports to the ruby cpu ports and
> # physmem, respectively
> #
> cpu.icache_port = system.ruby.cpu_ruby_ports[0].port
> cpu.dcache_port = system.ruby.cpu_ruby_ports[0].port
>
> # -----------------------
> # run simulation
> # -----------------------
>
43a87,90
> root.system.mem_mode = 'timing'
>
> # Not much point in this being higher than the L1 latency
> m5.ticks.setGlobalFrequency('1ns')