| simple-timing-mp.py (9321:7f0464326b2b) | simple-timing-mp.py (9790:ccc428657233) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 22 unchanged lines hidden (view full) --- 31m5.util.addToPath('../configs/common') 32from Caches import * 33 34nb_cores = 4 35cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] 36 37# system simulated 38system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus()) | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 22 unchanged lines hidden (view full) --- 31m5.util.addToPath('../configs/common') 32from Caches import * 33 34nb_cores = 4 35cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] 36 37# system simulated 38system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus()) |
| 39system.clock = '1GHz' |
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| 39 40# l2cache & bus 41system.toL2Bus = CoherentBus(clock = '2GHz') 42system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8) 43system.l2c.cpu_side = system.toL2Bus.master 44 45# connect l2c to membus 46system.l2c.mem_side = system.membus.slave --- 23 unchanged lines hidden --- | 40 41# l2cache & bus 42system.toL2Bus = CoherentBus(clock = '2GHz') 43system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8) 44system.l2c.cpu_side = system.toL2Bus.master 45 46# connect l2c to membus 47system.l2c.mem_side = system.membus.slave --- 23 unchanged lines hidden --- |