simple-timing-mp.py (9288:3d6da8559605) | simple-timing-mp.py (9321:7f0464326b2b) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 14 unchanged lines hidden (view full) --- 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Ron Dreslinski 28 29import m5 30from m5.objects import * | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 14 unchanged lines hidden (view full) --- 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Ron Dreslinski 28 29import m5 30from m5.objects import * |
31m5.util.addToPath('../configs/common') 32from Caches import * |
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31 | 33 |
32# -------------------- 33# Base L1 Cache 34# ==================== 35 36class L1(BaseCache): 37 hit_latency = 2 38 response_latency = 2 39 block_size = 64 40 mshrs = 4 41 tgts_per_mshr = 8 42 is_top_level = True 43 44# ---------------------- 45# Base L2 Cache 46# ---------------------- 47 48class L2(BaseCache): 49 block_size = 64 50 hit_latency = 20 51 response_latency = 20 52 mshrs = 92 53 tgts_per_mshr = 16 54 write_buffers = 8 55 | |
56nb_cores = 4 57cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] 58 59# system simulated 60system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus()) 61 62# l2cache & bus 63system.toL2Bus = CoherentBus(clock = '2GHz') | 34nb_cores = 4 35cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] 36 37# system simulated 38system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus()) 39 40# l2cache & bus 41system.toL2Bus = CoherentBus(clock = '2GHz') |
64system.l2c = L2(clock = '2GHz', size='4MB', assoc=8) | 42system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8) |
65system.l2c.cpu_side = system.toL2Bus.master 66 67# connect l2c to membus 68system.l2c.mem_side = system.membus.slave 69 70# add L1 caches 71for cpu in cpus: | 43system.l2c.cpu_side = system.toL2Bus.master 44 45# connect l2c to membus 46system.l2c.mem_side = system.membus.slave 47 48# add L1 caches 49for cpu in cpus: |
72 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 73 L1(size = '32kB', assoc = 4)) | 50 cpu.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1), 51 L1Cache(size = '32kB', assoc = 4)) |
74 # create the interrupt controller 75 cpu.createInterruptController() 76 # connect cpu level-1 caches to shared level-2 cache 77 cpu.connectAllPorts(system.toL2Bus, system.membus) 78 cpu.clock = '2GHz' 79 80system.system_port = system.membus.slave 81 82# connect memory to membus 83system.physmem.port = system.membus.master 84 85 86# ----------------------- 87# run simulation 88# ----------------------- 89 90root = Root( full_system = False, system = system ) 91root.system.mem_mode = 'timing' | 52 # create the interrupt controller 53 cpu.createInterruptController() 54 # connect cpu level-1 caches to shared level-2 cache 55 cpu.connectAllPorts(system.toL2Bus, system.membus) 56 cpu.clock = '2GHz' 57 58system.system_port = system.membus.slave 59 60# connect memory to membus 61system.physmem.port = system.membus.master 62 63 64# ----------------------- 65# run simulation 66# ----------------------- 67 68root = Root( full_system = False, system = system ) 69root.system.mem_mode = 'timing' |