simple-timing-mp.py (9036:6385cf85bf12) simple-timing-mp.py (9263:066099902102)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 20 unchanged lines hidden (view full) ---

29import m5
30from m5.objects import *
31
32# --------------------
33# Base L1 Cache
34# ====================
35
36class L1(BaseCache):
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 20 unchanged lines hidden (view full) ---

29import m5
30from m5.objects import *
31
32# --------------------
33# Base L1 Cache
34# ====================
35
36class L1(BaseCache):
37 latency = '1ns'
37 hit_latency = '1ns'
38 response_latency = '1ns'
38 block_size = 64
39 mshrs = 4
40 tgts_per_mshr = 8
41 is_top_level = True
42
43# ----------------------
44# Base L2 Cache
45# ----------------------
46
47class L2(BaseCache):
48 block_size = 64
39 block_size = 64
40 mshrs = 4
41 tgts_per_mshr = 8
42 is_top_level = True
43
44# ----------------------
45# Base L2 Cache
46# ----------------------
47
48class L2(BaseCache):
49 block_size = 64
49 latency = '10ns'
50 hit_latency = '10ns'
51 response_latency = '10ns'
50 mshrs = 92
51 tgts_per_mshr = 16
52 write_buffers = 8
53
54nb_cores = 4
55cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
56
57# system simulated

--- 32 unchanged lines hidden --- 		52 mshrs = 92
53 tgts_per_mshr = 16
54 write_buffers = 8
55
56nb_cores = 4
57cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
58
59# system simulated

--- 32 unchanged lines hidden ---