| simple-timing-mp.py (8931:7a1dfb191e3f) | simple-timing-mp.py (9036:6385cf85bf12) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 41 unchanged lines hidden (view full) --- 50 mshrs = 92 51 tgts_per_mshr = 16 52 write_buffers = 8 53 54nb_cores = 4 55cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] 56 57# system simulated | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 41 unchanged lines hidden (view full) --- 50 mshrs = 92 51 tgts_per_mshr = 16 52 write_buffers = 8 53 54nb_cores = 4 55cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] 56 57# system simulated |
| 58system = System(cpu = cpus, physmem = SimpleMemory(), membus = Bus()) | 58system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus()) |
| 59 60# l2cache & bus | 59 60# l2cache & bus |
| 61system.toL2Bus = Bus() | 61system.toL2Bus = CoherentBus() |
| 62system.l2c = L2(size='4MB', assoc=8) 63system.l2c.cpu_side = system.toL2Bus.master 64 65# connect l2c to membus 66system.l2c.mem_side = system.membus.slave 67 68# add L1 caches 69for cpu in cpus: --- 20 unchanged lines hidden --- | 62system.l2c = L2(size='4MB', assoc=8) 63system.l2c.cpu_side = system.toL2Bus.master 64 65# connect l2c to membus 66system.l2c.mem_side = system.membus.slave 67 68# add L1 caches 69for cpu in cpus: --- 20 unchanged lines hidden --- |