simple-timing-mp.py (8833:2870638642bd) | simple-timing-mp.py (8839:eeb293859255) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 47 unchanged lines hidden (view full) --- 56 57# system simulated 58system = System(cpu = cpus, physmem = PhysicalMemory(), membus = 59Bus()) 60 61# l2cache & bus 62system.toL2Bus = Bus() 63system.l2c = L2(size='4MB', assoc=8) | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 47 unchanged lines hidden (view full) --- 56 57# system simulated 58system = System(cpu = cpus, physmem = PhysicalMemory(), membus = 59Bus()) 60 61# l2cache & bus 62system.toL2Bus = Bus() 63system.l2c = L2(size='4MB', assoc=8) |
64system.l2c.cpu_side = system.toL2Bus.port | 64system.l2c.cpu_side = system.toL2Bus.master |
65 66# connect l2c to membus | 65 66# connect l2c to membus |
67system.l2c.mem_side = system.membus.port | 67system.l2c.mem_side = system.membus.slave |
68 69# add L1 caches 70for cpu in cpus: 71 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 72 L1(size = '32kB', assoc = 4)) 73 # connect cpu level-1 caches to shared level-2 cache 74 cpu.connectAllPorts(system.toL2Bus, system.membus) 75 cpu.clock = '2GHz' 76 | 68 69# add L1 caches 70for cpu in cpus: 71 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 72 L1(size = '32kB', assoc = 4)) 73 # connect cpu level-1 caches to shared level-2 cache 74 cpu.connectAllPorts(system.toL2Bus, system.membus) 75 cpu.clock = '2GHz' 76 |
77system.system_port = system.membus.port | 77system.system_port = system.membus.slave |
78 79# connect memory to membus | 78 79# connect memory to membus |
80system.physmem.port = system.membus.port | 80system.physmem.port = system.membus.master |
81 82 83# ----------------------- 84# run simulation 85# ----------------------- 86 87root = Root( full_system = False, system = system ) 88root.system.mem_mode = 'timing' | 81 82 83# ----------------------- 84# run simulation 85# ----------------------- 86 87root = Root( full_system = False, system = system ) 88root.system.mem_mode = 'timing' |