simple-timing-mp.py (4876:a18cedc19da5) simple-timing-mp.py (6978:ab05e20dc4a7)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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56# system simulated
57system = System(cpu = cpus, physmem = PhysicalMemory(), membus =
58Bus())
59
60# l2cache & bus
61system.toL2Bus = Bus()
62system.l2c = L2(size='4MB', assoc=8)
63system.l2c.cpu_side = system.toL2Bus.port
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 47 unchanged lines hidden (view full) ---

56# system simulated
57system = System(cpu = cpus, physmem = PhysicalMemory(), membus =
58Bus())
59
60# l2cache & bus
61system.toL2Bus = Bus()
62system.l2c = L2(size='4MB', assoc=8)
63system.l2c.cpu_side = system.toL2Bus.port
64system.l2c.num_cpus = nb_cores
64
65# connect l2c to membus
66system.l2c.mem_side = system.membus.port
67
68# add L1 caches
69for cpu in cpus:
70 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
71 L1(size = '32kB', assoc = 4))

--- 14 unchanged lines hidden --- 		65
66# connect l2c to membus
67system.l2c.mem_side = system.membus.port
68
69# add L1 caches
70for cpu in cpus:
71 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
72 L1(size = '32kB', assoc = 4))

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