| simple-timing-mp.py (3402:db60546818d0) | simple-timing-mp.py (4390:76bbcf725852) |
|---|---|
| 1# Copyright (c) 2006 The Regents of The University of Michigan | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan |
| 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the --- 57 unchanged lines hidden (view full) --- 67system.l2c.mem_side = system.membus.port 68 69# add L1 caches 70for cpu in cpus: 71 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 72 L1(size = '32kB', assoc = 4)) 73 # connect cpu level-1 caches to shared level-2 cache 74 cpu.connectMemPorts(system.toL2Bus) | 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the --- 57 unchanged lines hidden (view full) --- 67system.l2c.mem_side = system.membus.port 68 69# add L1 caches 70for cpu in cpus: 71 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 72 L1(size = '32kB', assoc = 4)) 73 # connect cpu level-1 caches to shared level-2 cache 74 cpu.connectMemPorts(system.toL2Bus) |
| 75 cpu.clock = '2GHz' |
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| 75 76# connect memory to membus 77system.physmem.port = system.membus.port 78 79 80# ----------------------- 81# run simulation 82# ----------------------- 83 84root = Root( system = system ) 85root.system.mem_mode = 'timing' | 76 77# connect memory to membus 78system.physmem.port = system.membus.port 79 80 81# ----------------------- 82# run simulation 83# ----------------------- 84 85root = Root( system = system ) 86root.system.mem_mode = 'timing' |