1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Ron Dreslinski
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32from Caches import *
33
34nb_cores = 4
35cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
36
37# system simulated
38system = System(cpu = cpus, physmem = SimpleMemory(), membus = CoherentBus())
39system.clock = '1GHz'
40
41# l2cache & bus
42system.toL2Bus = CoherentBus(clock = '2GHz')
43system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
44system.l2c.cpu_side = system.toL2Bus.master
45
46# connect l2c to membus
47system.l2c.mem_side = system.membus.slave
48
49# add L1 caches
50for cpu in cpus:
51 cpu.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
52 L1Cache(size = '32kB', assoc = 4))
53 # create the interrupt controller
54 cpu.createInterruptController()
55 # connect cpu level-1 caches to shared level-2 cache
56 cpu.connectAllPorts(system.toL2Bus, system.membus)
57 cpu.clock = '2GHz'
58
59system.system_port = system.membus.slave
60
61# connect memory to membus
62system.physmem.port = system.membus.master
63
64
65# -----------------------
66# run simulation
67# -----------------------
68
69root = Root( full_system = False, system = system )
70root.system.mem_mode = 'timing'