simple-timing-mp-ruby.py (9793:6e6cefc1db1f) simple-timing-mp-ruby.py (10120:f5ceb3c3edb6)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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78# CPUs frequency
79system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
80
81Ruby.create_system(options, system)
82
83# Create a separate clock domain for Ruby
84system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
85
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 69 unchanged lines hidden (view full) ---

78# CPUs frequency
79system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
80
81Ruby.create_system(options, system)
82
83# Create a separate clock domain for Ruby
84system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
85
86assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
86assert(options.num_cpus == len(system.ruby._cpu_ports))
87
88for (i, cpu) in enumerate(system.cpu):
89 # create the interrupt controller
90 cpu.createInterruptController()
91
92 #
93 # Tie the cpu ports to the ruby cpu ports
94 #
87
88for (i, cpu) in enumerate(system.cpu):
89 # create the interrupt controller
90 cpu.createInterruptController()
91
92 #
93 # Tie the cpu ports to the ruby cpu ports
94 #
95 cpu.connectAllPorts(system.ruby._cpu_ruby_ports[i])
95 cpu.connectAllPorts(system.ruby._cpu_ports[i])
96
97# -----------------------
98# run simulation
99# -----------------------
100
101root = Root( full_system=False, system = system )
102root.system.mem_mode = 'timing'
103
104# Not much point in this being higher than the L1 latency
105m5.ticks.setGlobalFrequency('1ns')
96
97# -----------------------
98# run simulation
99# -----------------------
100
101root = Root( full_system=False, system = system )
102root.system.mem_mode = 'timing'
103
104# Not much point in this being higher than the L1 latency
105m5.ticks.setGlobalFrequency('1ns')