| simple-timing-mp-ruby.py (8931:7a1dfb191e3f) | simple-timing-mp-ruby.py (9067:d0d9d10b3930) |
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| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 63 unchanged lines hidden (view full) --- 72# system simulated 73system = System(cpu = cpus, physmem = SimpleMemory()) 74 75Ruby.create_system(options, system) 76 77assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) 78 79for (i, cpu) in enumerate(system.cpu): | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 63 unchanged lines hidden (view full) --- 72# system simulated 73system = System(cpu = cpus, physmem = SimpleMemory()) 74 75Ruby.create_system(options, system) 76 77assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) 78 79for (i, cpu) in enumerate(system.cpu): |
| 80 # create the interrupt controller 81 cpu.createInterruptController() 82 |
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| 80 # 81 # Tie the cpu ports to the ruby cpu ports 82 # | 83 # 84 # Tie the cpu ports to the ruby cpu ports 85 # |
| 83 cpu.icache_port = system.ruby._cpu_ruby_ports[i].port 84 cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port | 86 cpu.connectAllPorts(system.ruby._cpu_ruby_ports[i]) |
| 85 86# ----------------------- 87# run simulation 88# ----------------------- 89 90root = Root( full_system=False, system = system ) 91root.system.mem_mode = 'timing' 92 93# Not much point in this being higher than the L1 latency 94m5.ticks.setGlobalFrequency('1ns') | 87 88# ----------------------- 89# run simulation 90# ----------------------- 91 92root = Root( full_system=False, system = system ) 93root.system.mem_mode = 'timing' 94 95# Not much point in this being higher than the L1 latency 96m5.ticks.setGlobalFrequency('1ns') |