simple-timing-mp-ruby.py (6870:5707ef3691b5) simple-timing-mp-ruby.py (6928:5bd33f7c26ea)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Ron Dreslinski
28
29import m5
30from m5.objects import *
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 14 unchanged lines hidden (view full) ---

23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Ron Dreslinski
28
29import m5
30from m5.objects import *
31from m5.defines import buildEnv
32from m5.util import addToPath
33import os, optparse, sys
31
34
35if buildEnv['FULL_SYSTEM']:
36 panic("This script requires system-emulation mode (*_SE).")
37
38# Get paths we might need
39config_path = os.path.dirname(os.path.abspath(__file__))
40config_root = os.path.dirname(config_path)
41m5_root = os.path.dirname(config_root)
42addToPath(config_root+'/configs/common')
43addToPath(config_root+'/configs/ruby')
44
45import Ruby
46
47parser = optparse.OptionParser()
48
49#
50# Set the default cache size and associativity to be very small to encourage
51# races between requests and writebacks.
52#
53parser.add_option("--l1d_size", type="string", default="256B")
54parser.add_option("--l1i_size", type="string", default="256B")
55parser.add_option("--l2_size", type="string", default="512B")
56parser.add_option("--l1d_assoc", type="int", default=2)
57parser.add_option("--l1i_assoc", type="int", default=2)
58parser.add_option("--l2_assoc", type="int", default=2)
59
60execfile(os.path.join(config_root, "configs/common", "Options.py"))
61
62(options, args) = parser.parse_args()
63
32nb_cores = 4
33cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
34
64nb_cores = 4
65cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
66
35import ruby_config
36ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
67# overwrite the num_cpus to equal nb_cores
68options.num_cpus = nb_cores
37
38# system simulated
69
70# system simulated
39system = System(cpu = cpus, physmem = ruby_memory, membus = Bus())
71system = System(cpu = cpus,
72 physmem = PhysicalMemory())
40
73
41# add L1 caches
42for cpu in cpus:
43 cpu.connectMemPorts(system.membus)
44 cpu.clock = '2GHz'
74system.ruby = Ruby.create_system(options, system.physmem)
45
75
46# connect memory to membus
47system.physmem.port = system.membus.port
76assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
48
77
78for (i, cpu) in enumerate(system.cpu):
79 #
80 # Tie the cpu ports to the ruby cpu ports
81 #
82 cpu.icache_port = system.ruby.cpu_ruby_ports[i].port
83 cpu.dcache_port = system.ruby.cpu_ruby_ports[i].port
49
50# -----------------------
51# run simulation
52# -----------------------
53
54root = Root( system = system )
55root.system.mem_mode = 'timing'
84
85# -----------------------
86# run simulation
87# -----------------------
88
89root = Root( system = system )
90root.system.mem_mode = 'timing'
91
92# Not much point in this being higher than the L1 latency
93m5.ticks.setGlobalFrequency('1ns')