| simple-timing-mp-ruby.py (6289:a9e7d19871b5) | simple-timing-mp-ruby.py (6870:5707ef3691b5) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 19 unchanged lines hidden (view full) --- 28 29import m5 30from m5.objects import * 31 32nb_cores = 4 33cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] 34 35import ruby_config | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 19 unchanged lines hidden (view full) --- 28 29import m5 30from m5.objects import * 31 32nb_cores = 4 33cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] 34 35import ruby_config |
| 36ruby_memory = ruby_config.generate("MI_example-homogeneous.rb", nb_cores) | 36ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores) |
| 37 38# system simulated 39system = System(cpu = cpus, physmem = ruby_memory, membus = Bus()) 40 41# add L1 caches 42for cpu in cpus: 43 cpu.connectMemPorts(system.membus) 44 cpu.clock = '2GHz' 45 46# connect memory to membus 47system.physmem.port = system.membus.port 48 49 50# ----------------------- 51# run simulation 52# ----------------------- 53 54root = Root( system = system ) 55root.system.mem_mode = 'timing' | 37 38# system simulated 39system = System(cpu = cpus, physmem = ruby_memory, membus = Bus()) 40 41# add L1 caches 42for cpu in cpus: 43 cpu.connectMemPorts(system.membus) 44 cpu.clock = '2GHz' 45 46# connect memory to membus 47system.physmem.port = system.membus.port 48 49 50# ----------------------- 51# run simulation 52# ----------------------- 53 54root = Root( system = system ) 55root.system.mem_mode = 'timing' |