1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 58 unchanged lines hidden (view full) --- 67nb_cores = 4 68cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] 69 70# overwrite the num_cpus to equal nb_cores 71options.num_cpus = nb_cores 72 73# system simulated 74system = System(cpu = cpus, physmem = SimpleMemory()) |
75system.clock = options.sys_clock |
76 77Ruby.create_system(options, system) 78 79assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) 80 81for (i, cpu) in enumerate(system.cpu): 82 # create the interrupt controller 83 cpu.createInterruptController() --- 15 unchanged lines hidden --- |