1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 74 unchanged lines hidden (view full) --- 83 84for (i, cpu) in enumerate(system.cpu): 85 # 86 # Tie the cpu ports to the ruby cpu ports 87 # 88 cpu.icache_port = system.ruby._cpu_ruby_ports[i].port 89 cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port 90 |
91# ----------------------- 92# run simulation 93# ----------------------- 94 95root = Root( system = system ) 96root.system.mem_mode = 'timing' 97 98# Not much point in this being higher than the L1 latency 99m5.ticks.setGlobalFrequency('1ns') |