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> from m5.defines import buildEnv
> from m5.util import addToPath
> import os, optparse, sys
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> if buildEnv['FULL_SYSTEM']:
> panic("This script requires system-emulation mode (*_SE).")
>
> # Get paths we might need
> config_path = os.path.dirname(os.path.abspath(__file__))
> config_root = os.path.dirname(config_path)
> m5_root = os.path.dirname(config_root)
> addToPath(config_root+'/configs/common')
> addToPath(config_root+'/configs/ruby')
>
> import Ruby
>
> parser = optparse.OptionParser()
>
> #
> # Set the default cache size and associativity to be very small to encourage
> # races between requests and writebacks.
> #
> parser.add_option("--l1d_size", type="string", default="256B")
> parser.add_option("--l1i_size", type="string", default="256B")
> parser.add_option("--l2_size", type="string", default="512B")
> parser.add_option("--l1d_assoc", type="int", default=2)
> parser.add_option("--l1i_assoc", type="int", default=2)
> parser.add_option("--l2_assoc", type="int", default=2)
>
> execfile(os.path.join(config_root, "configs/common", "Options.py"))
>
> (options, args) = parser.parse_args()
>
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< import ruby_config
< ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
---
> # overwrite the num_cpus to equal nb_cores
> options.num_cpus = nb_cores
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< system = System(cpu = cpus, physmem = ruby_memory, membus = Bus())
---
> system = System(cpu = cpus,
> physmem = PhysicalMemory())
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< # add L1 caches
< for cpu in cpus:
< cpu.connectMemPorts(system.membus)
< cpu.clock = '2GHz'
---
> system.ruby = Ruby.create_system(options, system.physmem)
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< # connect memory to membus
< system.physmem.port = system.membus.port
---
> assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
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> for (i, cpu) in enumerate(system.cpu):
> #
> # Tie the cpu ports to the ruby cpu ports
> #
> cpu.icache_port = system.ruby.cpu_ruby_ports[i].port
> cpu.dcache_port = system.ruby.cpu_ruby_ports[i].port
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>
> # Not much point in this being higher than the L1 latency
> m5.ticks.setGlobalFrequency('1ns')