simple-timing-mp-ruby.py (7034:6bf327b128c6) | simple-timing-mp-ruby.py (7570:417ef5d444bd) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 27 unchanged lines hidden (view full) --- 36 panic("This script requires system-emulation mode (*_SE).") 37 38# Get paths we might need 39config_path = os.path.dirname(os.path.abspath(__file__)) 40config_root = os.path.dirname(config_path) 41m5_root = os.path.dirname(config_root) 42addToPath(config_root+'/configs/common') 43addToPath(config_root+'/configs/ruby') | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 27 unchanged lines hidden (view full) --- 36 panic("This script requires system-emulation mode (*_SE).") 37 38# Get paths we might need 39config_path = os.path.dirname(os.path.abspath(__file__)) 40config_root = os.path.dirname(config_path) 41m5_root = os.path.dirname(config_root) 42addToPath(config_root+'/configs/common') 43addToPath(config_root+'/configs/ruby') |
44addToPath(config_root+'/configs/ruby/protocols') 45addToPath(config_root+'/configs/ruby/topologies') | |
46 47import Ruby 48 49parser = optparse.OptionParser() 50 51# | 44 45import Ruby 46 47parser = optparse.OptionParser() 48 49# |
52# Set the default cache size and associativity to be very small to encourage 53# races between requests and writebacks. | 50# Add the ruby specific and protocol specific options |
54# | 51# |
55parser.add_option("--l1d_size", type="string", default="256B") 56parser.add_option("--l1i_size", type="string", default="256B") 57parser.add_option("--l2_size", type="string", default="512B") 58parser.add_option("--l1d_assoc", type="int", default=2) 59parser.add_option("--l1i_assoc", type="int", default=2) 60parser.add_option("--l2_assoc", type="int", default=2) | 52Ruby.define_options(parser) |
61 62execfile(os.path.join(config_root, "configs/common", "Options.py")) 63 64(options, args) = parser.parse_args() 65 | 53 54execfile(os.path.join(config_root, "configs/common", "Options.py")) 55 56(options, args) = parser.parse_args() 57 |
58# 59# Set the default cache size and associativity to be very small to encourage 60# races between requests and writebacks. 61# 62options.l1d_size="256B" 63options.l1i_size="256B" 64options.l2_size="512B" 65options.l3_size="1kB" 66options.l1d_assoc=2 67options.l1i_assoc=2 68options.l2_assoc=2 69options.l3_assoc=2 70 |
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66nb_cores = 4 67cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] 68 69# overwrite the num_cpus to equal nb_cores 70options.num_cpus = nb_cores 71 72# system simulated | 71nb_cores = 4 72cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] 73 74# overwrite the num_cpus to equal nb_cores 75options.num_cpus = nb_cores 76 77# system simulated |
73system = System(cpu = cpus, 74 physmem = PhysicalMemory()) | 78system = System(cpu = cpus, physmem = PhysicalMemory()) |
75 | 79 |
76system.ruby = Ruby.create_system(options, system.physmem) | 80system.ruby = Ruby.create_system(options, system) |
77 78assert(options.num_cpus == len(system.ruby.cpu_ruby_ports)) 79 80for (i, cpu) in enumerate(system.cpu): 81 # 82 # Tie the cpu ports to the ruby cpu ports 83 # 84 cpu.icache_port = system.ruby.cpu_ruby_ports[i].port 85 cpu.dcache_port = system.ruby.cpu_ruby_ports[i].port 86 87# ----------------------- 88# run simulation 89# ----------------------- 90 91root = Root( system = system ) 92root.system.mem_mode = 'timing' 93 94# Not much point in this being higher than the L1 latency 95m5.ticks.setGlobalFrequency('1ns') | 81 82assert(options.num_cpus == len(system.ruby.cpu_ruby_ports)) 83 84for (i, cpu) in enumerate(system.cpu): 85 # 86 # Tie the cpu ports to the ruby cpu ports 87 # 88 cpu.icache_port = system.ruby.cpu_ruby_ports[i].port 89 cpu.dcache_port = system.ruby.cpu_ruby_ports[i].port 90 91# ----------------------- 92# run simulation 93# ----------------------- 94 95root = Root( system = system ) 96root.system.mem_mode = 'timing' 97 98# Not much point in this being higher than the L1 latency 99m5.ticks.setGlobalFrequency('1ns') |