simple-atomic.py (8931:7a1dfb191e3f) | simple-atomic.py (9036:6385cf85bf12) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 17 unchanged lines hidden (view full) --- 26# 27# Authors: Steve Reinhardt 28 29import m5 30from m5.objects import * 31 32system = System(cpu = AtomicSimpleCPU(cpu_id=0), 33 physmem = SimpleMemory(), | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 17 unchanged lines hidden (view full) --- 26# 27# Authors: Steve Reinhardt 28 29import m5 30from m5.objects import * 31 32system = System(cpu = AtomicSimpleCPU(cpu_id=0), 33 physmem = SimpleMemory(), |
34 membus = Bus()) | 34 membus = CoherentBus()) |
35system.system_port = system.membus.slave 36system.physmem.port = system.membus.master 37# create the interrupt controller 38system.cpu.createInterruptController() 39system.cpu.connectAllPorts(system.membus) 40system.cpu.clock = '2GHz' 41 42root = Root(full_system = False, system = system) | 35system.system_port = system.membus.slave 36system.physmem.port = system.membus.master 37# create the interrupt controller 38system.cpu.createInterruptController() 39system.cpu.connectAllPorts(system.membus) 40system.cpu.clock = '2GHz' 41 42root = Root(full_system = False, system = system) |