| simple-atomic.py (8801:1a84c6a81299) | simple-atomic.py (8839:eeb293859255) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 18 unchanged lines hidden (view full) --- 27# Authors: Steve Reinhardt 28 29import m5 30from m5.objects import * 31 32system = System(cpu = AtomicSimpleCPU(cpu_id=0), 33 physmem = PhysicalMemory(), 34 membus = Bus()) | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 18 unchanged lines hidden (view full) --- 27# Authors: Steve Reinhardt 28 29import m5 30from m5.objects import * 31 32system = System(cpu = AtomicSimpleCPU(cpu_id=0), 33 physmem = PhysicalMemory(), 34 membus = Bus()) |
| 35system.system_port = system.membus.port 36system.physmem.port = system.membus.port | 35system.system_port = system.membus.slave 36system.physmem.port = system.membus.master |
| 37system.cpu.connectAllPorts(system.membus) 38system.cpu.clock = '2GHz' 39 40root = Root(full_system = False, system = system) | 37system.cpu.connectAllPorts(system.membus) 38system.cpu.clock = '2GHz' 39 40root = Root(full_system = False, system = system) |