| simple-atomic-mp.py (9324:8650f0c53db5) | simple-atomic-mp.py (9790:ccc428657233) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 24 unchanged lines hidden (view full) --- 33 34nb_cores = 4 35cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] 36 37# system simulated 38system = System(cpu = cpus, 39 physmem = SimpleMemory(range = AddrRange('1024MB')), 40 membus = CoherentBus()) | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 24 unchanged lines hidden (view full) --- 33 34nb_cores = 4 35cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] 36 37# system simulated 38system = System(cpu = cpus, 39 physmem = SimpleMemory(range = AddrRange('1024MB')), 40 membus = CoherentBus()) |
| 41 | 41system.clock = '1GHz' |
| 42# l2cache & bus 43system.toL2Bus = CoherentBus(clock = '2GHz') 44system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8) 45system.l2c.cpu_side = system.toL2Bus.master 46 47# connect l2c to membus 48system.l2c.mem_side = system.membus.slave 49 --- 22 unchanged lines hidden --- | 42# l2cache & bus 43system.toL2Bus = CoherentBus(clock = '2GHz') 44system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8) 45system.l2c.cpu_side = system.toL2Bus.master 46 47# connect l2c to membus 48system.l2c.mem_side = system.membus.slave 49 --- 22 unchanged lines hidden --- |