| simple-atomic-mp.py (9321:7f0464326b2b) | simple-atomic-mp.py (9323:e22374824171) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 27 unchanged lines hidden (view full) --- 36 37# system simulated 38system = System(cpu = cpus, 39 physmem = SimpleMemory(range = AddrRange('1024MB')), 40 membus = CoherentBus()) 41 42# l2cache & bus 43system.toL2Bus = CoherentBus(clock = '2GHz') | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 27 unchanged lines hidden (view full) --- 36 37# system simulated 38system = System(cpu = cpus, 39 physmem = SimpleMemory(range = AddrRange('1024MB')), 40 membus = CoherentBus()) 41 42# l2cache & bus 43system.toL2Bus = CoherentBus(clock = '2GHz') |
| 44system.l2c = L2Caches(clock = '2GHz', size='4MB', assoc=8) | 44system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8) |
| 45system.l2c.cpu_side = system.toL2Bus.master 46 47# connect l2c to membus 48system.l2c.mem_side = system.membus.slave 49 50# add L1 caches 51for cpu in cpus: | 45system.l2c.cpu_side = system.toL2Bus.master 46 47# connect l2c to membus 48system.l2c.mem_side = system.membus.slave 49 50# add L1 caches 51for cpu in cpus: |
| 52 cpu.addPrivateSplitL1Caches(L1Caches(size = '32kB', assoc = 1), | 52 cpu.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1), |
| 53 L1Caches(size = '32kB', assoc = 4)) 54 # create the interrupt controller 55 cpu.createInterruptController() 56 # connect cpu level-1 caches to shared level-2 cache 57 cpu.connectAllPorts(system.toL2Bus, system.membus) 58 cpu.clock = '2GHz' 59 60# connect memory to membus 61system.physmem.port = system.membus.master 62 63# connect system port to membus 64system.system_port = system.membus.slave 65 66# ----------------------- 67# run simulation 68# ----------------------- 69 70root = Root( full_system = False, system = system ) 71root.system.mem_mode = 'atomic' | 53 L1Caches(size = '32kB', assoc = 4)) 54 # create the interrupt controller 55 cpu.createInterruptController() 56 # connect cpu level-1 caches to shared level-2 cache 57 cpu.connectAllPorts(system.toL2Bus, system.membus) 58 cpu.clock = '2GHz' 59 60# connect memory to membus 61system.physmem.port = system.membus.master 62 63# connect system port to membus 64system.system_port = system.membus.slave 65 66# ----------------------- 67# run simulation 68# ----------------------- 69 70root = Root( full_system = False, system = system ) 71root.system.mem_mode = 'atomic' |