simple-atomic-mp.py (9288:3d6da8559605) simple-atomic-mp.py (9321:7f0464326b2b)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 14 unchanged lines hidden (view full) ---

23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Ron Dreslinski
28
29import m5
30from m5.objects import *
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 14 unchanged lines hidden (view full) ---

23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Ron Dreslinski
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32from Caches import *
31
33
32# --------------------
33# Base L1 Cache
34# ====================
35
36class L1(BaseCache):
37 hit_latency = 2
38 response_latency = 2
39 block_size = 64
40 mshrs = 4
41 tgts_per_mshr = 8
42 is_top_level = True
43
44# ----------------------
45# Base L2 Cache
46# ----------------------
47
48class L2(BaseCache):
49 block_size = 64
50 hit_latency = 20
51 response_latency = 20
52 mshrs = 92
53 tgts_per_mshr = 16
54 write_buffers = 8
55
56nb_cores = 4
57cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
58
59# system simulated
60system = System(cpu = cpus,
61 physmem = SimpleMemory(range = AddrRange('1024MB')),
62 membus = CoherentBus())
63
64# l2cache & bus
65system.toL2Bus = CoherentBus(clock = '2GHz')
34nb_cores = 4
35cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
36
37# system simulated
38system = System(cpu = cpus,
39 physmem = SimpleMemory(range = AddrRange('1024MB')),
40 membus = CoherentBus())
41
42# l2cache & bus
43system.toL2Bus = CoherentBus(clock = '2GHz')
66system.l2c = L2(clock = '2GHz', size='4MB', assoc=8)
44system.l2c = L2Caches(clock = '2GHz', size='4MB', assoc=8)
67system.l2c.cpu_side = system.toL2Bus.master
68
69# connect l2c to membus
70system.l2c.mem_side = system.membus.slave
71
72# add L1 caches
73for cpu in cpus:
45system.l2c.cpu_side = system.toL2Bus.master
46
47# connect l2c to membus
48system.l2c.mem_side = system.membus.slave
49
50# add L1 caches
51for cpu in cpus:
74 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
75 L1(size = '32kB', assoc = 4))
52 cpu.addPrivateSplitL1Caches(L1Caches(size = '32kB', assoc = 1),
53 L1Caches(size = '32kB', assoc = 4))
76 # create the interrupt controller
77 cpu.createInterruptController()
78 # connect cpu level-1 caches to shared level-2 cache
79 cpu.connectAllPorts(system.toL2Bus, system.membus)
80 cpu.clock = '2GHz'
81
82# connect memory to membus
83system.physmem.port = system.membus.master
84
85# connect system port to membus
86system.system_port = system.membus.slave
87
88# -----------------------
89# run simulation
90# -----------------------
91
92root = Root( full_system = False, system = system )
93root.system.mem_mode = 'atomic'
54 # create the interrupt controller
55 cpu.createInterruptController()
56 # connect cpu level-1 caches to shared level-2 cache
57 cpu.connectAllPorts(system.toL2Bus, system.membus)
58 cpu.clock = '2GHz'
59
60# connect memory to membus
61system.physmem.port = system.membus.master
62
63# connect system port to membus
64system.system_port = system.membus.slave
65
66# -----------------------
67# run simulation
68# -----------------------
69
70root = Root( full_system = False, system = system )
71root.system.mem_mode = 'atomic'