| simple-atomic-mp.py (8931:7a1dfb191e3f) | simple-atomic-mp.py (9036:6385cf85bf12) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 43 unchanged lines hidden (view full) --- 52 write_buffers = 8 53 54nb_cores = 4 55cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] 56 57# system simulated 58system = System(cpu = cpus, 59 physmem = SimpleMemory(range = AddrRange('1024MB')), | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 43 unchanged lines hidden (view full) --- 52 write_buffers = 8 53 54nb_cores = 4 55cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] 56 57# system simulated 58system = System(cpu = cpus, 59 physmem = SimpleMemory(range = AddrRange('1024MB')), |
| 60 membus = Bus()) | 60 membus = CoherentBus()) |
| 61 62# l2cache & bus | 61 62# l2cache & bus |
| 63system.toL2Bus = Bus() | 63system.toL2Bus = CoherentBus() |
| 64system.l2c = L2(size='4MB', assoc=8) 65system.l2c.cpu_side = system.toL2Bus.master 66 67# connect l2c to membus 68system.l2c.mem_side = system.membus.slave 69 70# add L1 caches 71for cpu in cpus: --- 20 unchanged lines hidden --- | 64system.l2c = L2(size='4MB', assoc=8) 65system.l2c.cpu_side = system.toL2Bus.master 66 67# connect l2c to membus 68system.l2c.mem_side = system.membus.slave 69 70# add L1 caches 71for cpu in cpus: --- 20 unchanged lines hidden --- |