| simple-atomic-mp.py (8839:eeb293859255) | simple-atomic-mp.py (8876:44f8e7bb7fdf) |
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| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 56 unchanged lines hidden (view full) --- 65 66# connect l2c to membus 67system.l2c.mem_side = system.membus.slave 68 69# add L1 caches 70for cpu in cpus: 71 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 72 L1(size = '32kB', assoc = 4)) | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 56 unchanged lines hidden (view full) --- 65 66# connect l2c to membus 67system.l2c.mem_side = system.membus.slave 68 69# add L1 caches 70for cpu in cpus: 71 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), 72 L1(size = '32kB', assoc = 4)) |
| 73 # create the interrupt controller 74 cpu.createInterruptController() |
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| 73 # connect cpu level-1 caches to shared level-2 cache 74 cpu.connectAllPorts(system.toL2Bus, system.membus) 75 cpu.clock = '2GHz' 76 77# connect memory to membus 78system.physmem.port = system.membus.master 79 80# connect system port to membus 81system.system_port = system.membus.slave 82 83# ----------------------- 84# run simulation 85# ----------------------- 86 87root = Root( full_system = False, system = system ) 88root.system.mem_mode = 'atomic' | 75 # connect cpu level-1 caches to shared level-2 cache 76 cpu.connectAllPorts(system.toL2Bus, system.membus) 77 cpu.clock = '2GHz' 78 79# connect memory to membus 80system.physmem.port = system.membus.master 81 82# connect system port to membus 83system.system_port = system.membus.slave 84 85# ----------------------- 86# run simulation 87# ----------------------- 88 89root = Root( full_system = False, system = system ) 90root.system.mem_mode = 'atomic' |