simple-atomic-mp.py (9263:066099902102) | simple-atomic-mp.py (9288:3d6da8559605) |
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1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 20 unchanged lines hidden (view full) --- 29import m5 30from m5.objects import * 31 32# -------------------- 33# Base L1 Cache 34# ==================== 35 36class L1(BaseCache): | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 20 unchanged lines hidden (view full) --- 29import m5 30from m5.objects import * 31 32# -------------------- 33# Base L1 Cache 34# ==================== 35 36class L1(BaseCache): |
37 hit_latency = '1ns' 38 response_latency = '1ns' | 37 hit_latency = 2 38 response_latency = 2 |
39 block_size = 64 40 mshrs = 4 41 tgts_per_mshr = 8 42 is_top_level = True 43 44# ---------------------- 45# Base L2 Cache 46# ---------------------- 47 48class L2(BaseCache): 49 block_size = 64 | 39 block_size = 64 40 mshrs = 4 41 tgts_per_mshr = 8 42 is_top_level = True 43 44# ---------------------- 45# Base L2 Cache 46# ---------------------- 47 48class L2(BaseCache): 49 block_size = 64 |
50 hit_latency = '10ns' 51 response_latency = '10ns' | 50 hit_latency = 20 51 response_latency = 20 |
52 mshrs = 92 53 tgts_per_mshr = 16 54 write_buffers = 8 55 56nb_cores = 4 57cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] 58 59# system simulated 60system = System(cpu = cpus, 61 physmem = SimpleMemory(range = AddrRange('1024MB')), 62 membus = CoherentBus()) 63 64# l2cache & bus | 52 mshrs = 92 53 tgts_per_mshr = 16 54 write_buffers = 8 55 56nb_cores = 4 57cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] 58 59# system simulated 60system = System(cpu = cpus, 61 physmem = SimpleMemory(range = AddrRange('1024MB')), 62 membus = CoherentBus()) 63 64# l2cache & bus |
65system.toL2Bus = CoherentBus() 66system.l2c = L2(size='4MB', assoc=8) | 65system.toL2Bus = CoherentBus(clock = '2GHz') 66system.l2c = L2(clock = '2GHz', size='4MB', assoc=8) |
67system.l2c.cpu_side = system.toL2Bus.master 68 69# connect l2c to membus 70system.l2c.mem_side = system.membus.slave 71 72# add L1 caches 73for cpu in cpus: 74 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), --- 19 unchanged lines hidden --- | 67system.l2c.cpu_side = system.toL2Bus.master 68 69# connect l2c to membus 70system.l2c.mem_side = system.membus.slave 71 72# add L1 caches 73for cpu in cpus: 74 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), --- 19 unchanged lines hidden --- |