| simple-atomic-mp-ruby.py (6289:a9e7d19871b5) | simple-atomic-mp-ruby.py (6870:5707ef3691b5) |
|---|---|
| 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 20 unchanged lines hidden (view full) --- 29import m5 30from m5.objects import * 31 32 33nb_cores = 4 34cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] 35 36import ruby_config | 1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 20 unchanged lines hidden (view full) --- 29import m5 30from m5.objects import * 31 32 33nb_cores = 4 34cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] 35 36import ruby_config |
| 37ruby_memory = ruby_config.generate("MI_example-homogeneous.rb", nb_cores) | 37ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores) |
| 38 39# system simulated 40system = System(cpu = cpus, physmem = ruby_memory, membus = Bus()) 41 42# add L1 caches 43for cpu in cpus: 44 cpu.connectMemPorts(system.membus) 45 cpu.clock = '2GHz' 46 47# connect memory to membus 48system.physmem.port = system.membus.port 49 50 51# ----------------------- 52# run simulation 53# ----------------------- 54 55root = Root(system = system) 56root.system.mem_mode = 'atomic' | 38 39# system simulated 40system = System(cpu = cpus, physmem = ruby_memory, membus = Bus()) 41 42# add L1 caches 43for cpu in cpus: 44 cpu.connectMemPorts(system.membus) 45 cpu.clock = '2GHz' 46 47# connect memory to membus 48system.physmem.port = system.membus.port 49 50 51# ----------------------- 52# run simulation 53# ----------------------- 54 55root = Root(system = system) 56root.system.mem_mode = 'atomic' |