1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 33 unchanged lines hidden (view full) --- 42# add L1 caches 43for cpu in cpus: 44 cpu.connectAllPorts(system.membus) 45 cpu.clock = '2GHz' 46 47# connect memory to membus 48system.physmem.port = system.membus.port 49 |
50 51# ----------------------- 52# run simulation 53# ----------------------- 54 |
55root = Root(full_system = False, system = system) |
56root.system.mem_mode = 'atomic' |