1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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34nb_cores = 4
35cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ]
36
37import ruby_config
38ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
39
40# system simulated
41system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus())
42
43# add L1 caches
44for cpu in cpus:
45 cpu.connectAllPorts(system.membus)
46 cpu.clock = '2GHz'
47
48# connect memory to membus
49system.physmem.port = system.membus.master
50
51# Connect the system port for loading of binaries etc
52system.system_port = system.membus.slave
53
54# -----------------------
55# run simulation
56# -----------------------
57
58root = Root(full_system = False, system = system)
59root.system.mem_mode = 'atomic'