1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 63 unchanged lines hidden (view full) --- 72 check_flush = True 73 74# 75# create the tester and system, including ruby 76# 77tester = RubyTester(check_flush = check_flush, checks_to_complete = 100, 78 wakeup_frequency = 10, num_cpus = options.num_cpus) 79 |
80system = System(tester = tester, physmem = SimpleMemory(null = True)) |
81 82Ruby.create_system(options, system) 83 84assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) 85 86# 87# The tester is most effective when randomization is turned on and 88# artifical delay is randomly inserted on messages --- 10 unchanged lines hidden (view full) --- 99 tester.cpuInstPort = ruby_port.slave 100 101 # 102 # Tell the sequencer this is the ruby tester so that it 103 # copies the subblock back to the checker 104 # 105 ruby_port.using_ruby_tester = True 106 |
107# ----------------------- 108# run simulation 109# ----------------------- 110 111root = Root(full_system = False, system = system ) 112root.system.mem_mode = 'timing' 113 114# Not much point in this being higher than the L1 latency 115m5.ticks.setGlobalFrequency('1ns') |