1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 91 unchanged lines hidden (view full) --- 100 ruby_port.using_ruby_tester = True 101 102 # 103 # Ruby doesn't need the backing image of memory when running with 104 # the tester. 105 # 106 ruby_port.access_phys_mem = False 107 |
108# Connect the system port for loading of binaries etc 109system.system_port = system.ruby._sys_port_proxy.port 110 |
111# ----------------------- 112# run simulation 113# ----------------------- 114 |
115root = Root(full_system = False, system = system ) |
116root.system.mem_mode = 'timing' 117 118# Not much point in this being higher than the L1 latency 119m5.ticks.setGlobalFrequency('1ns') |