1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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92Ruby.create_system(options, False, system)
93
94# Create a separate clock domain for Ruby
95system.ruby.clk_domain = SrcClockDomain(clock = '1GHz',
96 voltage_domain = system.voltage_domain)
97
98assert(options.num_cpus == len(system.ruby._cpu_ports))
99
100#
101# The tester is most effective when randomization is turned on and
102# artifical delay is randomly inserted on messages
103#
104system.ruby.randomization = True
105
106for ruby_port in system.ruby._cpu_ports:
107 #
108 # Tie the ruby tester ports to the ruby cpu read and write ports
109 #
110 if ruby_port.support_data_reqs:
111 tester.cpuDataPort = ruby_port.slave
112 if ruby_port.support_inst_reqs:
113 tester.cpuInstPort = ruby_port.slave
114
115 #
116 # Tell the sequencer this is the ruby tester so that it
117 # copies the subblock back to the checker
118 #
119 ruby_port.using_ruby_tester = True
120
121# -----------------------
122# run simulation
123# -----------------------
124
125root = Root(full_system = False, system = system )
126root.system.mem_mode = 'timing'
127
128# Not much point in this being higher than the L1 latency
129m5.ticks.setGlobalFrequency('1ns')