1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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100 ruby_port.using_ruby_tester = True
101
102 #
103 # Ruby doesn't need the backing image of memory when running with
104 # the tester.
105 #
106 ruby_port.access_phys_mem = False
107
108# -----------------------
109# run simulation
110# -----------------------
111
112root = Root( system = system )
113root.system.mem_mode = 'timing'
114
115# Not much point in this being higher than the L1 latency
116m5.ticks.setGlobalFrequency('1ns')