realview-simple-timing.py (9288:3d6da8559605) realview-simple-timing.py (9310:aa7bf10e822a)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32import FSConfig
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 16 unchanged lines hidden (view full) ---

25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Steve Reinhardt
28
29import m5
30from m5.objects import *
31m5.util.addToPath('../configs/common')
32import FSConfig
33from Caches import *
33
34
34
35# --------------------
36# Base L1 Cache
37# ====================
38
39class L1(BaseCache):
40 hit_latency = 2
41 response_latency = 2
42 block_size = 64
43 mshrs = 4
44 tgts_per_mshr = 8
45 is_top_level = True
46
47# ----------------------
48# Base L2 Cache
49# ----------------------
50
51class L2(BaseCache):
52 block_size = 64
53 hit_latency = 20
54 response_latency = 20
55 mshrs = 92
56 tgts_per_mshr = 16
57 write_buffers = 8
58
59# ---------------------
60# I/O Cache
61# ---------------------
62class IOCache(BaseCache):
63 assoc = 8
64 block_size = 64
65 hit_latency = 50
66 response_latency = 50
67 mshrs = 20
68 size = '1kB'
69 tgts_per_mshr = 12
70 addr_ranges = [AddrRange(0, size='256MB')]
71 forward_snoops = False
72
73#cpu
74cpu = TimingSimpleCPU(cpu_id=0)
75#the system
76system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
77
78system.cpu = cpu
79
80#create the iocache
35#cpu
36cpu = TimingSimpleCPU(cpu_id=0)
37#the system
38system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
39
40system.cpu = cpu
41
42#create the iocache
81system.iocache = IOCache(clock = '1GHz')
43system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')])
82system.iocache.cpu_side = system.iobus.master
83system.iocache.mem_side = system.membus.slave
84
85#connect up the cpu and caches
86cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
87 L1(size = '32kB', assoc = 4),
88 L2(size = '4MB', assoc = 8))
89# create the interrupt controller
90cpu.createInterruptController()
91# connect cpu and caches to the rest of the system
92cpu.connectAllPorts(system.membus)
93# set the cpu clock along with the caches and l1-l2 bus
94cpu.clock = '2GHz'
95
96root = Root(full_system=True, system=system)
97m5.ticks.setGlobalFrequency('1THz')
98
44system.iocache.cpu_side = system.iobus.master
45system.iocache.mem_side = system.membus.slave
46
47#connect up the cpu and caches
48cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1),
49 L1(size = '32kB', assoc = 4),
50 L2(size = '4MB', assoc = 8))
51# create the interrupt controller
52cpu.createInterruptController()
53# connect cpu and caches to the rest of the system
54cpu.connectAllPorts(system.membus)
55# set the cpu clock along with the caches and l1-l2 bus
56cpu.clock = '2GHz'
57
58root = Root(full_system=True, system=system)
59m5.ticks.setGlobalFrequency('1THz')
60