realview-simple-timing.py (8883:c92153af04ac) realview-simple-timing.py (9036:6385cf85bf12)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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69
70#cpu
71cpu = TimingSimpleCPU(cpu_id=0)
72#the system
73system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
74
75system.cpu = cpu
76#create the l1/l2 bus
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 60 unchanged lines hidden (view full) ---

69
70#cpu
71cpu = TimingSimpleCPU(cpu_id=0)
72#the system
73system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
74
75system.cpu = cpu
76#create the l1/l2 bus
77system.toL2Bus = Bus()
77system.toL2Bus = CoherentBus()
78system.iocache = IOCache()
79system.iocache.cpu_side = system.iobus.master
80system.iocache.mem_side = system.membus.slave
81
82
83#connect up the l2 cache
84system.l2c = L2(size='4MB', assoc=8)
85system.l2c.cpu_side = system.toL2Bus.master

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78system.iocache = IOCache()
79system.iocache.cpu_side = system.iobus.master
80system.iocache.mem_side = system.membus.slave
81
82
83#connect up the l2 cache
84system.l2c = L2(size='4MB', assoc=8)
85system.l2c.cpu_side = system.toL2Bus.master

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