realview-simple-timing.py (8801:1a84c6a81299) realview-simple-timing.py (8839:eeb293859255)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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71cpu = TimingSimpleCPU(cpu_id=0)
72#the system
73system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
74
75system.cpu = cpu
76#create the l1/l2 bus
77system.toL2Bus = Bus()
78system.iocache = IOCache()
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 62 unchanged lines hidden (view full) ---

71cpu = TimingSimpleCPU(cpu_id=0)
72#the system
73system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
74
75system.cpu = cpu
76#create the l1/l2 bus
77system.toL2Bus = Bus()
78system.iocache = IOCache()
79system.iocache.cpu_side = system.iobus.port
80system.iocache.mem_side = system.membus.port
79system.iocache.cpu_side = system.iobus.master
80system.iocache.mem_side = system.membus.slave
81
82
83#connect up the l2 cache
84system.l2c = L2(size='4MB', assoc=8)
81
82
83#connect up the l2 cache
84system.l2c = L2(size='4MB', assoc=8)
85system.l2c.cpu_side = system.toL2Bus.port
86system.l2c.mem_side = system.membus.port
85system.l2c.cpu_side = system.toL2Bus.master
86system.l2c.mem_side = system.membus.slave
87
88#connect up the cpu and l1s
89cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
90 L1(size = '32kB', assoc = 4))
91# connect cpu level-1 caches to shared level-2 cache
92cpu.connectAllPorts(system.toL2Bus, system.membus)
93cpu.clock = '2GHz'
94
95root = Root(full_system=True, system=system)
96m5.ticks.setGlobalFrequency('1THz')
97
87
88#connect up the cpu and l1s
89cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
90 L1(size = '32kB', assoc = 4))
91# connect cpu level-1 caches to shared level-2 cache
92cpu.connectAllPorts(system.toL2Bus, system.membus)
93cpu.clock = '2GHz'
94
95root = Root(full_system=True, system=system)
96m5.ticks.setGlobalFrequency('1THz')
97