realview-simple-timing.py (8713:2f1a3e335255) realview-simple-timing.py (8801:1a84c6a81299)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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87
88#connect up the cpu and l1s
89cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
90 L1(size = '32kB', assoc = 4))
91# connect cpu level-1 caches to shared level-2 cache
92cpu.connectAllPorts(system.toL2Bus, system.membus)
93cpu.clock = '2GHz'
94
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 78 unchanged lines hidden (view full) ---

87
88#connect up the cpu and l1s
89cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
90 L1(size = '32kB', assoc = 4))
91# connect cpu level-1 caches to shared level-2 cache
92cpu.connectAllPorts(system.toL2Bus, system.membus)
93cpu.clock = '2GHz'
94
95root = Root(system=system)
95root = Root(full_system=True, system=system)
96m5.ticks.setGlobalFrequency('1THz')
97
96m5.ticks.setGlobalFrequency('1THz')
97