realview-simple-timing-dual.py (8713:2f1a3e335255) realview-simple-timing-dual.py (8801:1a84c6a81299)
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 80 unchanged lines hidden (view full) ---

89for c in cpus:
90 c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
91 L1(size = '32kB', assoc = 4))
92 # connect cpu level-1 caches to shared level-2 cache
93 c.connectAllPorts(system.toL2Bus, system.membus)
94 c.clock = '2GHz'
95
96
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 80 unchanged lines hidden (view full) ---

89for c in cpus:
90 c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
91 L1(size = '32kB', assoc = 4))
92 # connect cpu level-1 caches to shared level-2 cache
93 c.connectAllPorts(system.toL2Bus, system.membus)
94 c.clock = '2GHz'
95
96
97root = Root(system=system)
97root = Root(full_system=True, system=system)
98m5.ticks.setGlobalFrequency('1THz')
99
98m5.ticks.setGlobalFrequency('1THz')
99